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| advanced W682510/w682310 dual-channel voiceband codecs publ i c at i on rel e ase dat e : may 2003 - 1 - revi si on 0.35
W682510/w682310 1. general description the W682510 and w682310 are general-purpose dual channel pcm codecs with pin-selectable - law or a-law companding. the device is compliant wi th the itu g.712 specification. it operates from a single power supply (+5v for the W682510, +3v fo r the w682310) and is available in 20-pin pdip (W682510 only), ssop, and 24-pin sop package options . functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters requi red for pcm systems. the filters are compliant with itu g.712 s pecification. the W682510 and w682310 performance is specified over the industrial temperature range of ?40 c to + 8 5 c. the W682510 includes an on-chip precision voltage re ference and receive output buffer amplifiers, capable of driving 600 ? loads (line transformers.) the analog se ction is fully differential, reducing noise and improving the power supply rejection rati o. the data transfer protocol supports either parallel or serial synchronous communicati ons for pcm applications. the W682510 and w682310 have a build in pll that eliminates the need for a master clock and automat ically determines the division ratio for the required internal clock. for fast evaluation and prototyping purposes , the W682510dk & w682310dk development kits are available. 2. features ? single power supply o 4.5v to 5.5v (W682510) o 2.7v to 3.8v (w682310) ? typical power dissipation of 35 mw, power-down mode of 5 w ? fully-differential analog circuit design ? on-chip precision reference- o W682510: 1.73v for a 0.8 dbm 0tlp at 600 ? o w682310: 1.41v reference for a 0tlp of ?3.8 dbm into 1200 ? pin-selectable -law and a-law companding (compliant with itu g.711) ? codec a/d and d/a filtering compliant with itu g.712 ? industrial temperature range (?40 c to +85 c) ? three packages: 20-pin ssop, 20-pin pdip, and 24-pin sop applications ? digital telephone systems ? central office equipment (gateways, switches, routers) ? pbx sys t ems (gateways , switc hes ) ? pabx/soho sys t ems ? hands free system ? speakerphone devices ? voip terminals ? enterprise phones ? isdn terminals ? analog line cards - 2 - W682510/w682310 3. block diagram pl l /a - la w code c filt e r 1 /a - la w code c filt e r 2 v ssa v ssd pu i v dd p o w e r c o nd it io ning ro 1 ao 1 - ai1 vol t ag e r e f e r e n c e v re f ro 2 ao 2 - ai2 /a - law bc l k pc m in t er f ac fs r fs t pc m t 2 pc m t 1 pc m r 1 pc m r 2 p c mms da t a t1 da t a r 1 da t a t2 da t a r 2 pl l /a - la w code c filt e r 1 /a - la w code c filt e r 2 p o w e r c o nd it io ning p o w e r c o nd it io ning ro 1 ao 1 - ai1 ro 1 ao 1 - ai1 vol t ag e r e f e r e n c e v re f ro 2 ao 2 - ai2 ro 2 ao 2 - ai2 /a - law bc l k p c m i n te r f ace fs r fs t pc m t 2 pc m t 1 pc m r 1 pc m r 2 p c mms da t a t1 da t a r 1 da t a t2 da t a r 2 publ i c at i on rel e ase dat e : may 2003 - 3 - revi si on 0.35 W682510/w682310 4. table of contents 1. general d escript i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......... 2 1. general d escript i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......... 2 2. feat u r e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................... 2 3. block diag ram ............................................................................................................... ............... 3 4. table of cont ents ........................................................................................................... ........... 4 5. pin conf iguratio n ........................................................................................................... ............ 6 6. pin des cription ............................................................................................................. ................ 7 7. functional descript ion ...................................................................................................... ...... 8 7.1. transmit path ............................................................................................................................. 8 7.1.1. ai1, ai 2, ao1-, ao2- .................................................................................................... .......... 9 7.1.2. pcmt1 ................................................................................................................... ................ 9 7.1.3. pcmt2 ................................................................................................................... .............. 10 7.2. receive path ............................................................................................................................ 10 7.2.1. ro 1, ro2 ................................................................................................................ ............. 10 7.2.2. pcmr1 ................................................................................................................... .............. 11 7.2.3. pcmr2 ................................................................................................................... .............. 11 7.3. power signals .......................................................................................................................... 11 7.3.1. v dd ............................................................................................................................... ......... 11 7.3.2. v ssa ............................................................................................................................... ........ 11 7.3.3. v ssd ............................................................................................................................... ........ 11 7.3.4. v ref ............................................................................................................................... ........ 12 7.3.5. pui ..................................................................................................................... ................... 12 7.4. pcm interface .......................................................................................................................... 12 7.4.1. /a-law ......................................................................................................................... ....... 12 7.4.2. bclk .................................................................................................................... ................ 13 7.4.3. fsr ..................................................................................................................... .................. 13 7.4.4. fst ..................................................................................................................... .................. 13 7.4.5. pcmms ................................................................................................................... ............. 13 7.5. power state modes ................................................................................................................. 13 7.5.1. power save mode ......................................................................................................... ....... 13 7.5.2. power down mode ......................................................................................................... ...... 14 7.5.3. power save/down output pin s t ate ..................................................................................... 14 8. timing diagram s ............................................................................................................. ............. 15 9. absolute maxi mum ratin gs ................................................................................................... 1 9 - 4 - W682510/w682310 10. electrical characteristi cs .............................................................................................. 20 10.1. general parameters W682510 4.5v ? 5.5v ................................................................ 20 10.2. general parameters w682310 2.7v ? 3.8v ................................................................ 20 10.3. analog signal level and gain parameters ....................................................................... 22 10.4. analog distortion and noise parameters .......................................................................... 24 10.5. analog input and output amplifier parameters ................................................................ 25 10.6. digital i/o ............................................................................................................................... .2 6 11. typical appl ication circuit ................................................................................................ 29 12. package drawing and dimens ions ................................................................................... 31 12.1. 20l (pdip) plastic dual inline package dimensions (W682510 only) ......................... 31 12.2. 20l ssop ? 209 mil shrink small outline package dimensions .................................. 32 12.3. 24 sop ? 300 mil .................................................................................................................. 33 13. ordering informat ion ....................................................................................................... .... 34 14. version history ............................................................................................................ ............ 35 publ i c at i on rel e ase dat e : may 2003 - 5 - revi si on 0.35 W682510/w682310 5. pin configuration 24 23 22 21 20 19 18 17 16 14 w682310 dual ch annel co dec 1 2 3 4 5 6 7 8 9 11 sop v re f ro2 nc ro1 pu i pc m m s nc v dd v ss d fsr pc m r 2 pc m r 1 ai2 ao2 - ao1 - ai1 nc a- / law v ss a nc bclk fst pc m t 2 pc m t 1 10 15 12 13 20 19 18 17 16 15 14 13 12 w682310 dual ch annel co dec 1 2 3 4 5 6 7 8 9 p d ip (W682510 only), ssop v re f ro2 ro1 pu i pc m m s v dd v ss d fsr pc m r 2 pc m r 1 ai2 ao2 - ao1 - ai1 ro2 ro1 pu i pc m m s v dd v ss d fsr pc m r 2 pc m r 1 ai2 ao2 - ao1 - ai1 a / - law v ss a bclk fst pc m t 2 pc m t 1 10 11 W682510/ W682510/ - 6 - W682510/w682310 6. pin description pin nam e pin # sso p pdip pin # so p functionality (ch1 = channel 1, ch2 = channel 2) v ref 1 1 this pin is used to bypass the signal ground. it needs to be decoupled to v ss through a 0.1 f ceramic decoupling capacitor. no external loads should be tied to this pin. ro2 2 2 ch2 non-inverting output of the receive smoothing filter. this pin can typically drive a 600 load (W682510) or 1200 load (w682310). ro1 3 4 ch1 non-inverting output of the receive smoothing filter. this pin can typically drive a 600 load (W682510) or 1200 load (w682310).. pui 4 5 power up input signal. when this pin is high (tied to v dd ) the part is powered up. when low (tied to v ss ) the part is powered down. pcmms 5 6 pcm mode select input (serial or paralle l data interface) high = parallel, low = s e rial v dd 6 8 power supply. this pin should be decoupled to v ss with a 0.1 f ceramic capacitor. v ssd 7 9 this is the digital supply ground. this pin should be connected to 0v. fsr 8 10 8 khz frame sync input for the pcm re ceive section. it can also be connected to the fst pin when transmit and re ceive are synchronous operations. pcmr2 9 11 ch2 pcm input data receive pin. the data needs to be synchronous with the fsr and bclk pins. pcmr1 10 12 ch1 pcm input data receive pin. the data needs to be synchronous with the fsr and bclk pins. pcmt1 11 13 ch1 pcm output data transmit pin. the output data is synchronous with the fst and bclk pins. pcmt2 12 14 ch2 pcm output data transmit pin. the output data is synchronous with the fst and bclk pins. fst 13 15 8 khz transmit frame sync input. this pi n synchronizes the transmit data bytes. bclk 14 16 pcm transmit and receive bit clock input pin for ch1 and ch2 transmit. v ssa 15 18 this is the analog supply ground. th is pin should be connected to 0v. /a-law 16 19 compander mode select pin. -law companding is selected when this pin is low (tied to v ss .) a-law companding is selected when pin is high (tied to v dd .) ai1 17 21 ch1 non-inverting input of the fi rst gain stage in the transmit path. ao 1- 18 22 ch1 inverting analog output of the fi rst gain stage in the transmit path. ao 2- 19 23 ch2 inverting analog output of the fi rst gain stage in the transmit path ai2 20 24 ch2 non-inverting input of the fi rst gain stage in the transmit path. publ i c at i on rel e ase dat e : may 2003 - 7 - revi si on 0.35 W682510/w682310 7. functional description W682510/w682310 is a single-rail, dual channel pcm codec for voiceband applications. the codec complies with the specifications of t he itu-t g.712 recommendation. the codec includes two c o mplete -law and a-law companders. the -law and a-law companders are designed to comply with the specifications of the itu-t g.711 recommendation. the block diagram in section 3 shows the main components of the W682510/w682310. the chip consists of a pcm interface, whic h can process the data in parallel or serial formats. the pll of the chip provides the internal clock signals and synchr onizes the codec sample rate with the external frame sync frequency. the power-conditioning block prov ides the internal power supply for the digital and the analog section, while the voltage referenc e block provides a precision analog ground voltage for the analog signal processing. 8 /a - c ont r o l 8 b i t /a - la w dac ro 1 - + s m o o th in g f ilt e r 1 b f c = 3400 h z s m o o th in g f ilt e r 1 a b u ffe r 1 av= 1 da t a r1 8 /a - c ont r o l 8 b i t /a - la w dac ro 2 - + s m o o th in g f ilt e r 2 b f c = 3400 h z s m o o th in g f ilt e r 2 a b u ffe r 2 av= 1 da t a r2 8 /a - c ont r o l ai 2 ao 2 - - + ant i - al i a si n f ilt e r 2 b f c = 3400 h z ant i - al i a si n f ilt e r 2 a f c = 200 h z hi g h p a s s f ilt e r 8 b i t /a - la w adc da t a t1 8 /a - c ont r o l ai 1 ao 1 - - + ant i - al i a si n f ilt e r 1 b f c = 3400 h z ant i - al i a si n f ilt e r 1 a f c = 200 h z hi g h p a s s f ilt e r 8 b i t /a - la w adc da t a t1 8 /a - c ont r o l 8 b i t /a - la w dac ro 1 - + s m o o th in g f ilt e r 1 b f c = 3400 h z s m o o th in g f ilt e r 1 a b u ffe r 1 av= 1 da t a r1 8 /a - c ont r o l 8 b i t /a - la w dac ro 1 - + s m o o th in g f ilt e r 1 b s m o o th in g f ilt e r 1 b f c = 3400 h z s m o o th in g f ilt e r 1 a f c = 3400 h z s m o o th in g f ilt e r 1 a b u ffe r 1 av= 1 da t a r1 8 /a - c ont r o l 8 b i t /a - la w dac ro 2 - + s m o o th in g f ilt e r 2 b s m o o th in g f ilt e r 2 b f c = 3400 h z s m o o th in g f ilt e r 2 a f c = 3400 h z s m o o th in g f ilt e r 2 a b u ffe r 2 av= 1 da t a r2 8 /a - c ont r o l ai 2 ai 2 ao 2 - - + ant i - al i a si ng f ilt e r 2 b ant i - f ilt e r 2 b f c = 3400 h z ant i - al i a si ng f ilt e r 2 a f c = 3400 h z ant i - f ilt e r 2 a f c = 200 h z hi g h p a s s f ilt e r 8 b i t /a - la w adc da t a t2 8 /a - c ont r o l ai 1 ai 1 ao 1 - - + ant i - al i a si ng f ilt e r 1 b ant i - f ilt e r 1 b f c = 3400 h z ant i - al i a si ng f ilt e r 1 a f c = 3400 h z ant i - f ilt e r 1 a f c = 200 h z hi g h p a s s f ilt e r 8 b i t /a - la w adc da t a t1 figure 7.1: the W682510 and w682310 signal path 7.1. t ra nsmit p at h the a-to-d path of the codec contains an analog i nput amplifier with externally configurable gain setting (see application examples in section 11). t he transmit amplifier output is the input to the encoder section. the output of the input amplifier is fed through a lo w-pass filter to prevent aliasing at the switched capacitor 3.4 khz low pass filter. the 3.4 khz swit ched capacitor low pass filt er prevents aliasing of input signals above 4 khz, due to the sampling at 8 khz. the output of the 3.4 khz low pass filter is filtered by a high pass filter with a 200 hz cut-o ff frequency. the filters are designed according to the recommendations in the g.712 itu-t s pecification. from the output of the high pass filter the signal is digitized. the signal is converted into a comp ressed 8-bit digital representation with either -law or a- - 8 - W682510/w682310 law format. the -law or a-law format is pin-selectable through the /a-law pin. the compression format can be selected according to table 7.1. table 7.1: pin-selectable compression format /a-law pin format v dd (high) a-law v ssa (low) -law the digital 8-bit -law or a-law samples are fed to the pcm interface for serial or parallel transmission at the sample rate suppli ed by the external frame sync fst. 7.1.1. ai1, ai2, ao1-, ao2- ai1 and ai2 are the transmit analog inputs for channels 1 and 2. ao1- and ao2- are the transmit level feedback for channels 1 and 2. ai1 and ai2 are inverti ng inputs for the op-amps. ao1- and ao2- are connected to the outputs of the op -amps and are used to set the level, as illustrated below. when ai1 and ai2 are not used, connect ai1 to ao1- and ai 2 to ao2-. during power saving mode and power down mode, the ao1- and ao2- outputs are tied weakly to v ssa on the W682510 or are high impedance on the w682310 (see table on page 14). ao 1 - ai 1 - + c1 r1 r2 ao 2 - ai 2 - + c2 r3 r4 ch 1 a n al o g i nput ch 2 a n al o g i nput ga i n = r 2 / r 1 10 r2 > 20 k o h m ga i n = r 4 / r 3 10 r4 > 20 k o h m ao 1 - ai 1 - + c1 r1 r2 ao 2 - ai 2 - + c2 r3 r4 ao 1 - ai 1 - + c1 r1 r2 ao 1 - ai 1 - + c1 r1 r2 ao 2 - ai 2 - + c2 r3 r4 ao 2 - ai 2 - + c2 r3 r4 ch 1 a n al o g i nput ch 2 a n al o g i nput ga i n = r 2 / r 1 10 r2 > 20 k o h m ga i n = r 4 / r 3 10 r4 > 20 k o h m 7.1.2. pcmt1 the pcm signal output of channel 1 when the paralle l mode is selected. the pcm output signal is sent from pcmt1 in a sequential order, synchroni zing with the rising edge of the bclk signal. the msb may be output at the rising edge of the fst signal, based on the timing between bclk and fst. this output pin is in a high impedance state except during 8-bit pcm output. it is also in a high impedance state during power-saving st ate or power-down. when serial operation is selected, this pin is configured to be the output of the serial multip lexed two channel pcm signal. a pull-up resistor must publ i c at i on rel e ase dat e : may 2003 - 9 - revi si on 0.35 W682510/w682310 be connected to this pin , as it is an open drain outpu t. this device is compatible with the itu-t coding law and output coding format recommendation. table 7.15: pcm codes for zero and full scale -law a-law lev e l sign bit chord bits step bits sign bit chord bits step bits + ful l scal e 1 000 0000 1 010 1010 + z e r o 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 - z e r o 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 - ful l scal e 0 000 0000 0 010 1010 7.1.3. pcmt2 the pcm signal output for channel 2 when the paralle l mode is selected. the pcm output signal is sent from pcmt2 in a sequential order, synchroni zed with the rising edge of the bclk signal. the msb may be output at the rising edge of the fst signal, based on the timing between bclk and fst. this pin is in a high impedance state except duri ng 8-bit pcm output. it is also in a high impedance state during power-saving state or power-down. when the serial operation is selected, this pin is left open. a pull-up resistor must be connected to this pi n , as it is an open drain output. this device is compatible with the itu-t coding law and output coding format recommendation. 7.2. r eceive p at h the 8-bit digital input samples for the d-to-a path are serially shifted in by the pcm interface and converted to parallel data bits. during every cycle of the frame sync fsr, the parallel data bits are fed through the pin-selectable -law or a-law expander and converted to analog samples. the mode of expansion is selected by the /a-law pin as shown in table 7.2. the analog samples are filtered by a low-pass smoothing filter with a 3.4 khz cut-off fr equency, according to the itu-t g.712 specification. a sin(x)/x compensation is integrated with the low pass smoothing filter. the out put of this filter is buffered to provide the receive output signal ro. 7.2.1. ro1, ro2 ro1 and ro2 are the receive analog outputs for c hannel 1 and channel 2. the output signal of the W682510 has an amplitude of 3.46 vpp (2.03 v pp for w682310) around the signal ground voltage (v ref ). when the digital pcm signal of +3 dbm0 is pr esented to pcmr1 or pcmr2, it can drive a load of 600 ohms or more at 5 v supply voltage for the W682510 and 1200 ohms at 3v supply for the w682310. during power saving mode, these outputs are at the voltage level of v ref with a high impedance. these outputs have a f eature that reduces audio ?pop? noises when switching between active and inactive states and back. - 10 - W682510/w682310 7.2.2. pcmr1 the pcm signal input for channel 1 when in the par allel mode. d/a conversion is performed on the serial pcm signal input to this pin. the fsr si gnal, synchronous with the serial pcm signal, and the bclk signal, processes the code. t hen the analog output is output from the ro1 pin. the data rate of the pcm signal is equal to the frequency of the bclk signal. the pcm signal is shifted in on the falling edge of the bclk signal. it is latched into the internal 8-bit register. the start of the pcm data (msb) is synchr onized with the rising edge of fsr. in the serial mode, this pin is not used and should be connected to gnd (0v). 7.2.3. pcmr2 pcm signal input for channel 2 when the parallel mode is selected. d/a conversion is performed with the serial pcm signal input to this pin, the fs r signal, synchronous with the serial pcm signal, and the bclk signal, and then the analog out put is output from the ro2 pi n. the data rate of the pcm signal is equal to the frequency of the bclk signal. t he pcm signal is shifted at the falling edge of the bclk signal and latched into the internal register w hen shifted by eight bits. the start of the pcm data (msb) is identified at the rising edge of fsr. in t he serial mode this pin is used for the two channel multiplexed pcm signal input. 7.3. p ower s igna l s 7.3.1. v dd the power supply for the analog and digital parts of the W682510 must be 5v +/- 10% and 2.7v to 3.8v for the w682310. this supply voltage is connected to the v dd pin. the v dd pin needs to be decoupled to ground through a 0.1 f ceramic capacitor. a power supply for an analog circuit in the system to which the device is applied should be used. a bypass capacitor of 0.1 f to 1 f with good high-frequency characteristics (low esr) and a capac itor of 10 f to 20 f should be connected between this pin and the v ssa pin if needed. 7.3.2. v ssa ground for the analog signal circuits. this ground is separate from the digital signal ground. the v ssa pin must be connected to the v ssd pin on the printed circuit board to make a common ground. however, it?s advised to connect t he pcb traces of these pins at the main supply hookup of the pcb and run the v ssa and v ssd traces separately to the device. 7.3.3. v ssd ground for the digital signal circuits. this ground is separate from the analog signal ground. the v ssd pin must be connected to the v ssa pin on the printed circuit board to make a common ground. however, it?s advised to connect t he pcb traces of these pins at the main supply hookup of the pcb and run the v ssa and v ssd traces separately to the device publ i c at i on rel e ase dat e : may 2003 - 11 - revi si on 0.35 W682510/w682310 7.3.4. v ref this pin carries the signal ground voltage le vel and requires a bypass capacitor. a 0.1 f ceramic (with low esr for good high frequency response) capacitor needs to be connected between the v ssa pin and the v ref pin. 7.3.5. pui power up input signal. when the pui pin is set to logic ?0? level, the codec will go into power down mode. 7.4. pcm i nterfa ce the pcm interface is controlled by pins pcmms , bclk, fsr & fst. the input data is received through the pcmr pin and the output data is trans mitted through the pcmt pin. the modes of operation of the interface are shown in table 7.2. table 7.2: pcm interface mode selections pcmms pcm mode data av ailable v dd [high] parallel mode ch1 data on pcmt1 & pcmr1 ch2 data on pcmt2 and pcmr2 (same timing as ch1) v ss [low] serial mode ch1 data followed by ch2 receive data on pcmr2 (total 16 bits) ch1 data followed by ch2 transmit data on pcmt1 (total 16 bits) 7.4.1. /a-law this pin selects the desired companding law. the codec will operate in the -law when this pin is at a logic ?0? level and in the a-law when at a logic ?1? level. the codec operates -law if the pin is left open, since this pin is internally pulled down. table 7.25: pin-selectable compression format /a-law pin format high (v dd ) a - l a w low (v ss ), floating -law - 12 - W682510/w682310 7.4.2. bclk this is the shift clock signal input for the pcmr1, pcmr2, pcmt1, and pcmt2 signals. the frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048 or 200 khz. setting this signal to a steady logic ?1? or ?0? sets both transmit and receive circuits to the power saving state. 7.4.3. fsr this is the receive synchronizing signal input. the required eight-bits of pcm data are selected from the pcm data signal to the pcmr1 and pcmr2 pins by the receive synchronizing signal. all timing signals in the receive section are synchronized by this synchronizi ng signal. this signal must be in phase with the bclk. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics. this device can operate in the range of 6 khz to 9 khz, but the electrical characteristics specified in the data sheet are not guaranteed. 7.4.4. fst the transmit synchronizing signal input. the pcm out put signal from pcmt1 and pcmt2 is sent in synchronization with this transmit synchronizi ng signal. this fst signal triggers the pll and synchronizes all timing signals of the transmit secti on. the synchronizing signal must be in phase with bclk. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics. this device can operate in the range of 6 khz to 9 khz sample rate s, but the electrical characteristics are not guaranteed. setting this signal to logic high or lo w drives both transmit and receive circuits to power saving state. 7.4.5. pcmms the control signal for mode selection of the pcm input and output. when this signal is high, the pcm input and output are in the parallel mode. the pcm data of ch1 and ch2 is input to pcmr1 and pcmr2, and output from pcmt1 and pcmt2, with t he same timing. when this signal is at a low level, the pcm input and output are in the serial mode. the pcm data of ch1 and ch2 is input to pcmr2 and output from pcmt1 as two serial 8-bit bytes. 7.5. p ower s ta te m odes 7.5.1. pow e r sav e mode in the power save mode, all internal analog circuits except the internal reference are powered down. the codec automatically enters the power save mode when the fst or bclk signal is set to digital ?1? or digital ?0?; upon power up with fst and bclk signals present, it will take 2 to 10 milliseconds for the internal pll to lock. in addition to the pll lock-in time, the analog outputs will be set to the internal signal ground for 1 millisecond. this will avoid power up g litches at the outputs. the digital open drain outputs will remain at high impedance during this power up delay. publ i c at i on rel e ase dat e : may 2003 - 13 - revi si on 0.35 W682510/w682310 7.5.2. pow e r dow n mode when the power up indicator pin, pui, is set low all in ternal circuits will go into the power down state. it will take 2 to 10 milliseconds for the pll to lo ck when operation is resumed with the fst and bclk signals applied and pui set high. an additional 1-m illisecond delay is used to set the analog outputs to the signal ground reference in order to avoid power up glitches. the digital open drain outputs will remain at high impedance during this power up delay. 7.5.3. pow e r sav e /dow n output pin state the following table shows the stat es of the output pins in the power save or power down mode. table 7.5: output pin states output pin product name ao1-, a02- ro1, ro2 w 6 8 2 5 1 0 v ssa s i g n a l g r o u n d w682310 high z signal ground - 14 - W682510/w682310 8. timing diagrams figur e 8- 1a. t r an sm it side s e r i al m ode t i min g ( p cm m s =0) fs t pcm t 1 d0 d1 d2 d3 d4 d5 d6 ms b d0 d1 d2 d3 d4 d5 d6 ms b bcl k figur e 8 - 1b. rec e iv e s i de serial m o de t i m i ng (p cm m s =0 ) fs r pcm r 2 d0 d1 d2 d3 d4 d5 d6 ms b d0 d1 d2 d3 d4 d5 d6 ms b bcl k chan nel 1 t r ans m i t pcm data chan nel 2 t r ans m i t pcm data chan nel 2 rece iv e p c m data chan nel 1 rece iv e p c m data figure 8.1: serial mode pcm timing f i gur e 8 - 2a . t r an smit s i d e p a ra l l e l m o de t i min g ( p c m m s =1) fst pc m t 1 pc m t 2 d0 d1 d2 d3 d4 d5 d6 ms b bc l k f i gur e 8 - 2b . r e ceiv e s i d e p a rallel m o de t i ming ( p c m m s =1) fsr pc m r 1 pc m r 2 d0 d1 d2 d3 d4 d5 d6 ms b bc l k figure 8.2: parallel mode pcm timing publ i c at i on rel e ase dat e : may 2003 - 15 - revi si on 0.35 W682510/w682310 fi g u re 8 - 3 a . bu rs t m o de w i th se ri al t i m i n g (pcm m s =0 ) fst fsr pcm t 1 pcm r 2 d0 d1 d2 d3 d4 d5 d6 ms b d0 d1 d2 d3 d4 d5 d6 ms b bcl k fi g u re 8 - 3 b . bu rs t m o de w i th pa ra ll e l t i m i ng (pcm m s =1) fst fsr pcm t x pcm r x d0 d1 d2 d3 d4 d5 d6 ms b bcl k c h ann el 1 p c m d a ta c h ann el 2 p c m d a ta 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 1 12 1 3 14 1 5 1 6 17 figure 8.3: burst mode pcm timing - 16 - W682510/w682310 table 8.1: pcm synchronization parameters symbol description min typ max unit f fs fst, fsr frequency --- 8 - - - k h z t ws fst, fsr pulse width 1 --- 7 t bclk t j fst, fsr allowable jitter 0 --- 500 nsec f bclk bclk f r e q u e n c y 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 khz d c bclk duty c y c l e 4 0 5 0 6 0 % t ir fsr, fst, bclk, pcmr 1, pcmr2, pui, pcmms input rise time - - - - - - 5 0 n s e c t if fsr, fst, bclk, pcmr 1, pcmr2, pui, pcmms input fall time - - - - - - 5 0 n s e c bclk t ws 8 7 6 5 4 3 2 1 fs r fs t t j t bc l k =1/ f bc l k t fs =1/ f fs d c t ir t if figure 8.4: pcm synchronization parameters publ i c at i on rel e ase dat e : may 2003 - 17 - revi si on 0.35 W682510/w682310 table 8.2: pcm timing parameters symbol description min typ max unit t ws fst, fsr pulse width t bclk - - - 1 0 0 sec t xs bclk low to fst high setup time 100 --- --- nsec t sx fst high to bclk low hold time 100 --- --- nsec t sd pcmt1, pcmt2 output delay; cl = 100 pf 20 --- 200 nsec t xd1 pcmt1, pcmt2 output delay; cl = 100 pf 20 --- 200 nsec t xd2 pcmt1, pcmt2 output delay; cl = 100 pf 20 --- 200 nsec t xd3 pcmt1, pcmt2 output delay; cl = 100 pf 20 --- 200 nsec t rs bclk low to fsr high setup time 100 --- --- nsec t sr fsr high to bclk low hold time 100 --- --- nsec t ds pcmr1, pcmr2 data in setup time 100 --- --- nsec t dh pcmr1, pcmr2 data in hold time 100 --- --- nsec r tl pcmt1, pcmt2 pull-up resistor 500 --- --- ohm c tl pcmt1, pcmt2 load capacitance --- --- 100 pf f i g u r e 8- 5a. tr ans mi t t i mi ng fs t pc mt1 pc mt2 bc lk ms b d0 d1 d2 d3 d4 d5 d6 t ws t sx t xs t xd 1 t sd t xd 2 t xd 3 f i g u r e 8- 5b. r e c e i v e t i mi ng fs r pc mr 1 pc mr 2 bc lk 11 ms b d0 d1 d2 d3 d4 d5 d6 t ws t sr t rs t dh t ds 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 figure 8.5 pcm timing parameters - 18 - W682510/w682310 9. absolute maximum ratings table 9.1: absolute maximum ratings (packaged parts) condition value junction temperature 150 0 c storage temperature range -65 0 c to + 150 0 c voltage applied to any pin (v ss - 0.3v) to (v dd + 0.3v) voltage applied to any pin (input current limited to +/-20 ma) (v ss ? 1.0v) to (v dd + 1.0v) lead temperature (soldering ? 10 seconds) 300 0 c v dd - v ss -0.5v to + 6 v note : exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. functional operation is not implied at these conditions. table 9.2: operating conditions (packaged parts) condition value industrial operating temperature -40 0 c to + 8 5 0 c supply voltage (v dd ) W682510 5v +4.5v to + 5 . 5 v supply voltage (v dd ) w682310 3v +2.7v to + 3 . 8 v ground voltage (v ss ) 0 v publ i c at i on rel e ase dat e : may 2003 - 19 - revi si on 0.35 W682510/w682310 10. electrical characteristics 10.1. g enera l p a r a m eters W682510 4.5v ? 5.5v sy mbol parameters conditions min (2) ty p (1) max (2) units v il input low voltage 0.0 0.8 v v ih input high voltage 2.2 v dd v v ol p c m t 1 , p c m t 2 o u t p u t low voltage r pullup >500 0 . 0 0 . 2 0 . 4 v i dd v dd current (operating) - adc + dac no load, no signal 7 1 4 m a i sb v dd current (standby) fst or bclk =off; pui=v dd 8 0 0 1 3 0 0 a i pd v dd current (power down) pui= v ss 1 1 0 a i il input low leakage current v ss W682510/w682310 gain variation vs. level t one (1020 hz relative to ?10 dbm0) g lt + 3 to ?40 dbm0 -40 to ?50 dbm0 -50 to ?55 dbm0 --- --- --- -0.3 -0.5 -1.2 +0 .3 +0 .5 +1 .2 -0.3 -0.5 -1.2 +0 .3 +0 .5 +1 .2 db publ i c at i on rel e ase dat e : may 2003 - 23 - revi si on 0.35 W682510/w682310 10.4. a na log d istortion a nd n oise p ar am e t e r s W682510: v dd =5v 10%; v ss =0v ; t a =-40 c to + 8 5 c; all analog signals referred to v ref ; w682310: v dd = 2 .7v to 3.8v; v ss =0v ; t a =-40 c to + 8 5 c; all analog signals referred to v ref ; transmit (a/d) receive (d/a) parameter sym. condition min. typ. max. min. typ. max. unit total dis t ortion vs . level tone (1020 hz, -law, c-message weighted) d lt +3 db m0 0 dbm0 to -30 dbm0 -40 dbm0 -45 dbm0 36 36 29 25 --- --- --- --- --- --- --- --- 34 36 30 25 --- --- --- --- --- --- --- --- dbc total dis t ortion vs . level tone (1020 hz, a-law, psophometric weighted) d lt a + 3 db m 0 0 dbm0 to -30 dbm0 -40 dbm0 -45 dbm0 36 36 29 25 --- --- --- --- --- --- --- --- 34 36 30 25 --- --- --- --- --- --- --- --- dbp spurious out-of-band at ro- (300 hz to 3400 hz @ 0dbm0) d spo 4600 hz to 7600 hz 7600 hz to 8400 hz 8400 hz to 100000 hz --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- -30 -40 -30 db spurious in-band (700 hz to 1100 hz @ 0dbm0) d spi 300 to 3000 hz --- - - - - 4 7 --- - - - - 4 7 db intermodulation distortion (300 hz to 3400 hz ?4 to ?21 dbm0 d im t w o t o n e s - - - - - - - 4 1 - - - - - - - 4 1 d b crosstalk (1020 hz @ 0dbm0) d xt - - - - - - - 7 5 - - - - - - - 7 5 d b m 0 channel to channel crosstalk (1020 hz @ 0dbm0) d xt ch - - - - - - - 7 5 - - - - - - - 7 5 d b m 0 absolute group delay abs 1 6 0 0 h z - - - - - - 3 6 0 - - - - - - 2 4 0 sec group delay dis t ortion (relative to group delay @ 1200 hz) d 500 hz 600 hz 1000 hz 2600 hz 2800 hz --- --- --- --- --- --- --- --- --- --- 750 380 130 130 750 --- --- --- --- --- --- --- --- --- --- 750 370 120 120 750 sec idle channel noise n idl -law; c-message a-law; psophometric --- --- --- --- 5 -69 --- --- --- --- 13 -79 dbrnc dbm0p - 24 - W682510/w682310 10.5. a na log i nput a nd o utput a mplifier p ar am e t e r s W682510: v dd =5v 10%; v ss =0v ; t a =-40 c to + 8 5 c; all analog signals referred to v ref ; w682310: v dd = 2 .7v to 3.8v; v ss =0v ; t a =-40 c to + 8 5 c; all analog signals referred to v ref ; parameter sym. condition min. typ. max. unit. ai1, ai2 input offset voltage v off,ai u n i t y g a i n - - - - - - 20 mv ai1, ai2 input resistance r in,ai ai1, ai2 to v re f 1 0 - - - - - - m ao1-, ao2- output amplitude v ad w 6 8 2 5 1 0 w 682310 0 - - - 3 . 4 1.4 vpp ao1-, ao2- load resistance r load 2 0 - - - - - - k ao1-, ao2- load capacitance c load a o 1 - , a o 2 - - - - - - - 3 0 p f ro1, ro2 load resistance r load w 6 8 2 5 1 0 w 682310 0.6 1.2 - - - - - - k ro1, ro2 load capacitance c load r o 1 , r o 2 - - - - - - 5 0 p f ro1, ro2 output amplitude v oro w 6 8 2 5 1 0 w 682310 - - - - - - 3 . 4 2.0 vpp ro1, ro2 output offset voltage v off,ro ro to v re f - - - - - - 100 mv signal ground voltage to v ssa v re f v dd /2 ? 0.1 v dd /2 v dd /2+ 0.1 v pow e r supply rejection ratio (0 to 100 khz to v dd , c-message) psrr t r ansmit; 50 mvpp receive; 50 mvpp -- -- 40 40 --- --- dbc publ i c at i on rel e ase dat e : may 2003 - 25 - revi si on 0.35 W682510/w682310 10.6. d igita l i/o table 10.61: -law encode decode characteristics digital code d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 normalized encode decision levels s i g n c h o r d c h o r d chor d s t e p s t e p s t e p s t e p normalized decode levels 1 0 0 0 0 0 0 0 8 0 3 1 : 1 0 0 0 1 1 1 1 4 1 9 1 : 1 0 0 1 1 1 1 1 2 0 7 9 : 1 0 1 0 1 1 1 1 1 0 2 3 : 1 0 1 1 1 1 1 1 4 9 5 : 1 1 0 0 1 1 1 1 2 3 1 : 1 1 0 1 1 1 1 1 9 9 : 1 1 1 0 1 1 1 1 3 3 : 1 1 1 1 1 1 1 0 2 1 1 1 1 1 1 1 1 0 8159 7903 : 4319 4063 : 2143 2015 : 1055 991 : 511 479 : 239 223 : 103 95 : 35 31 : 3 1 0 notes: sign bit = 0 for negative values, sign bit = 1 for positive values - 26 - W682510/w682310 table 10.62: a-law encode decode characteristics digital code d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 normalized encode decision levels s i g n c h o r d c h o r d chor d s t e p s t e p s t e p s t e p normalized decode levels 1 0 1 0 1 0 1 0 4 0 3 2 : 1 0 1 0 0 1 0 1 2 1 1 2 : 1 0 1 1 0 1 0 1 1 0 5 6 : 1 0 0 0 0 1 0 1 5 2 8 : 1 0 0 1 0 1 0 1 2 6 4 : 1 1 1 0 0 1 0 1 1 3 2 : 1 1 1 0 0 1 0 1 6 6 : 1 1 0 1 0 1 0 1 1 4096 3968 : 2048 2048 : 1088 1024 : 544 512 : 272 256 : 136 128 : 68 64 : 2 0 notes: 1. sign bit = 0 for negative values, sign bit = 1 for positive values 2. digital code includes inversion of all even number bits publ i c at i on rel e ase dat e : may 2003 - 27 - revi si on 0.35 W682510/w682310 table 10.63: pcm codes for zero and full scale -law a-law lev e l sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) + full scale 1 000 0000 1 010 1010 + zero 1 111 1111 1 101 0101 - zero 0 111 1111 0 101 0101 - full scale 0 000 0000 0 010 1010 table 10.64: pcm codes for 0dbm0 output -law a-law sample sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 2 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 3 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 4 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 5 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0 6 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 7 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 8 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0 - 28 - W682510/w682310 11. typical application circuit 0. 1 f 1 f v dd bit cl o c k i nput p c m 2 ch. s e r i al o u tput 1k a i 2 24 ao 2 - 23 ao 1 - 22 a i 1 21 nc 20 w 682510/ w 2310 1 vr e f 2 r o 2 3 nc 4 r o 1 5 pui 6 p c mms 7 nc 8 v dd 9 v ssd 11 pc m r 2 so p 10 f s r 12 pc m r 1 a/ 19 v ssa 18 nc 17 bc l k 1 6 pc m t 2 14 fs t 1 5 pc m t 1 13 pc m t 1 13 channe l an a l o g i npu t channe l an a l o g i npu t channe l 2 an a l o g o u tput channe l 1 an a l o g o u tput pow e r up i nput f r am e s y nc i nput p c m 2 ch s e r i al i nput v dd figure 11.1: application circui t for serial mode operation publ i c at i on rel e ase dat e : may 2003 - 29 - revi si on 0.35 W682510/w682310 0.1 f 1 f v dd b i t c l ock i n pu t pc m c h 1 se ri a l ou tp u t a i 2 24 ao 2 - 23 ao 1 - 22 a i 1 21 nc 20 w 682510/w 6 8 2310 1 vr e f 2 r o 2 3 nc 4 r o 1 5 p u i 6 p c mms 7 nc 8 v dd 9 v ssd 11 p c m r 2 so p 10 f s r 12 p c m r 1 a/ 19 v ssa 18 nc 17 bc l k 1 6 pcm t 2 14 fs t 1 5 pcm t 1 13 ch an n e l 1 an a l o g in pu t ch an n e l 2 an a l o g ou tp u t ch an n e l 1 an a l o g ou tp u t po we r u p in pu t f r am e s y n c i n p u t pc m c h 1 se ri a l in p u t 1k v dd 1k v dd pc m c h 2 se ri a l in p u t 1k pc m c h 2 se ri a l ou tp u t figure 11.2: application circui t for parallel mode operation - 30 - W682510/w682310 12. package drawing and dimensions 12.1. 20l (pdip) p la stic d ua l i nline p a cka ge d imensions (W682510 only ) seating a e 2 a 1 1 1 2 b b 1 d 1 e s a e 1 1 a base e c l dimension (mm) dimension (inch) sy mbol m i n . n o m . max . m i n . n o m . max . a - - 4 . 4 5 - - 0 . 1 7 5 a 1 0 . 2 5 - - 0 . 0 1 0 - - a 2 3 9 1 8 3 . 3 0 3 . 4 3 0 . 1 2 5 0 . 1 3 0 0 . 1 3 5 b 0 . 4 1 0 . 4 6 0 . 5 6 0 . 0 1 6 0 . 0 1 8 0 . 0 2 2 b 1 1 . 4 7 1 . 5 2 1 . 6 3 0 . 0 5 8 0 . 0 6 0 0 . 0 6 4 c 0 . 2 0 0 . 2 5 0 . 3 6 0 . 0 0 8 0 . 0 1 0 0 . 0 1 4 d - 2 0 . 0 6 2 6 . 4 2 - 1 . 0 2 6 1 . 0 4 6 e 7 . 3 7 7 . 6 2 7 . 8 7 0 . 2 9 0 0 . 3 0 0 0 . 3 1 0 e 1 6 . 2 2 6 . 3 5 6 . 4 8 0 . 2 4 5 0 . 2 5 0 0 . 2 5 5 e 1 2 . 2 9 2 . 5 4 2 . 7 9 0 . 0 9 0 0 . 1 0 0 0 . 1 1 0 l 3 . 0 5 3 . 3 0 3 . 5 6 0 . 1 2 0 0 . 1 3 0 0 . 1 4 0 0 o - 1 5 o 0 o - 1 5 o e a 8 . 5 1 9 . 0 2 9 . 5 3 0 . 3 3 5 0 . 3 5 5 0 . 3 7 5 s - - 1 . 9 1 - - 0 . 0 7 5 publ i c at i on rel e ase dat e : may 2003 - 31 - revi si on 0.35 W682510/w682310 - 32 - 12.2. 20l ssop ? 209 mil s hrink s ma ll o utline p a cka ge d imensions d 1 2 dtea i l e h e 1 1 dimension (mm) dimension (inch) sy mbol m i n . n o m . max . m i n . n o m . max . a - - 2 . 0 0 - - 0 . 0 7 9 a 1 0 . 0 5 - - 0 . 0 0 2 - - a 2 1 . 6 5 1 . 7 5 1 . 8 5 0 . 0 6 5 0 . 0 6 9 - b 0 . 2 2 - 0 . 3 8 0 . 0 0 9 - 0 . 0 1 5 c 0 . 0 9 - 0 . 2 5 0 . 0 0 4 - 0 . 0 1 0 d 6 . 9 0 7 . 2 0 7 . 5 0 0 . 2 7 2 0 . 2 8 3 0 . 2 9 5 e 5 . 0 0 5 . 3 0 5 . 6 0 0 . 1 9 7 0 . 2 0 9 0 . 2 2 0 h e 7 . 4 0 7 . 8 0 8 . 2 0 0 . 2 9 1 0 . 3 0 7 0 . 3 2 3 e - 0 . 6 5 - - 0 . 0 2 5 6 - l 0 . 5 5 0 . 7 5 0 . 9 5 0 . 0 2 1 0 . 0 3 0 0 . 0 3 7 l 1 - 1 . 2 5 - - 0 . 0 5 0 - y - - 0 . 1 0 - - 0 . 0 0 4 0 0 o - 8 o 0 - 8 o e y b a a a sea t i ng l l deta i l sea t i ng b W682510/w682310 12.3. 24 sop ? 300 mil l o c e h a1 a e b d sea t i ng p l a n e y 0. 25 ga u g e pl a n e dimension (mm) dimension (inch) sy mbol m i n . m a x . m i n . max . a 2 . 3 5 2 . 6 5 0 . 0 9 3 0 . 1 0 4 a 1 0 . 1 0 0 . 3 0 0 . 0 0 4 0 . 0 1 2 b 0 . 3 3 0 . 5 1 0 . 0 1 3 0 . 0 2 0 c 0 . 2 3 0 . 3 2 0 . 0 0 9 0 . 0 1 3 e 7 . 4 0 7 . 6 0 0 . 2 9 1 0 . 2 9 9 d 1 5 . 2 0 1 5 . 6 0 0 . 5 9 8 0 . 6 1 4 e 1.27 bsc 0.050 bsc h e 1 0 . 0 0 1 0 . 6 5 0 . 3 9 4 0 . 4 1 9 y 0 . 1 0 0 . 0 0 4 l 0 . 1 0 1 . 2 7 0 . 0 1 6 0 . 0 5 0 0 0 o 8 o 0 8 o publ i c at i on rel e ase dat e : may 2003 - 33 - revi si on 0.35 W682510/w682310 13. ordering information product number descriptor key product family w 682510 pr oduct W682510 _ package ty pe: e = 20-lead plastic dual inline package (pdip) s = 24-lead plastic small outline package (sop) r = 20-lead plastic small outline package (ssop) when ordering W682510 series devices, pleas e refer to the following part numbers. part number W682510e W682510s W682510r product family w 682310 pr oduct w682310 _ package ty pe: s = 24-lead plastic small outline package (sop) r = 20-lead plastic small outline package (ssop) when ordering w682310 series devices, pleas e refer to the following part numbers. part number w682310s w682310r for the latest product information, access winbond?s worldwide website at http://www.winbond-usa.com - 34 - W682510/w682310 14. version history version date page description 0.31 mar 2003 all preliminary specifications 0 . 3 4 a p r . 2 0 0 3 u p d a t e s 0.35 may 2003 frequency response updated publ he a dqua r t e r s winbond ele c t r onic s cor por a t ion a m e r ic a winbond ele c t r onic s ( s ha ngha i) lt d. no. 4, creation rd. iii 2727 north first street, san jose, 27f, 299 y an an w . rd. shanghai, science-based industrial park, ca 95134, u.s.a. 200336 china hsinchu, t a iw an t e l: 1-408-9436666 t e l: 86-21-62365999 t e l: 886-3-5770066 fax: 1-408-5441797 fax: 86-21-62356998 fax: 886-3-5665577 http:// www.wi nbond-usa.com/ http:// www.wi nbond.com .tw/ t a ipe i of f i c e winbond ele c t r onic s cor por a t ion j a p a n winbond ele c t r onic s ( h .k.) lt d. 9f, no. 480, pueiguang rd. 7f daini-ueno bldg. 3-7-18 unit 9-15, 22f, m illennium city , neihu district shiny o kohama kohokuku, no. 378 kw un t ong rd., t a ipei, 114 t a iw an y o kohama, 222-0033 kow l oon, hong kong t e l: 886-2-81777168 t e l: 81-45-4781881 t e l: 852-27513100 fax: 886-2-87153579 fax: 81-45-4781800 fax: 852-27552064 pl ease note that al l data and speci f i c ati o ns ar e subj ect to chang e w i thout noti c e. al l the tr ademar ks of pr oducts and compani e s menti oned i n thi s datasheet bel ong to thei r r e specti v e ow ner s. t h i s pr oduct i n cor por ates super fl ash? technol o g y l i c ensed fr om sst . i c at i on rel e ase dat e : may 2003 - 35 - revi si on 0.35 |
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